1. Field of the Invention
The present invention relates to an ESD/EOS protection circuit and related integrated circuit, and more particularly, to an ESD/EOS protection circuit and related integrated circuit with improved EOS (Electrical Over Stress) performance.
2. Description of the Prior Art
Electrical charges caused by electrostatic discharge (ESD) effects and Electrical Over-Stress (EOS) effects may destroy internal circuits of an integrated circuit. In order to solve the problem caused by the ESD/EOS effect, an ESD/EOS protection circuit is set to couple with at least an I/O port and a voltage source (VDD/VSS). When the ESD effect occurs, the ESD/EOS protection circuit has to provide a low-resistance discharge path so that the ESD pulses with extremely high peak values can be discharged through the low-resistance discharge path without destroying the internal circuit. An EOS (Electrical Over-Stress) occurs when a voltage greater than the maximum specified voltage is applied to any portion of an electronic device. This excess voltage will often cause excess current to flow along some electrical paths in the electronic device. If the current remains too long, heating of the electronic device will occur and result in a permanent damage. In addition, when the internal circuits of the electronic device normally operate, the ESD/EOS protection circuit should not affect operations and functions of the internal circuits.
The traditional ESD/EOS protection circuit is designed for preventing leakage from the I/O port to the VDD or VSS port in normal usage. But if we use a clamping circuit between the I/O port and the VDD port, a leakage current may occur, which is not allowed in some specifications. Hence, the clamping circuit can be applied between the I/O port and the VSS port only. MOS transistors are generally and widely used in ESD/EOS protection circuits, and the induced snap-back effect can therefore supply a low-resistance static discharge path. However, unstable system power supply would produce unexpected voltage pulse (i.e. EOS) to damage the ESD/EOS protection circuit through the I/O port, especially the MOS transistor's gate oxide.